1. Field of the Inventive Concept
Example embodiments of inventive concepts relate to a test method of a semiconductor device and/or a semiconductor test apparatus.
2. Description of the Related Art
A dynamic random access memory (DRAM) cell includes a capacitor for storing charges and a transistor to access the capacitor. The charges (i.e., data) stored in the capacitor may be lost with the lapse of time.
A VRT cell is a cell whose data retention time (i.e. charge retention time) is not constant. In the related art, a VRT cell is detected by writing data to a DRAM cell and testing multiple times if data is lost or not after a specific period of time has passed. Even if the DRAM cell is determined to be a normal cell in the first test cycle, it may be determined to be a defective cell due to data loss in the second test cycle. After repeatedly performing tests, the DRAM cell exhibiting changed test results is determined to be a VRT cell.
However, since the data retention time of the VRT cell is not constant, as described above, even if the DRAM cell is determined to be a normal cell in the two test cycles, it may be determined to be a defective cell in a third test cycle.
Therefore, according to the related art test method, it is difficult to eliminate all VRT cells whose data retention time varies. In addition, since multiple test repetitions are performed to obtain an optimum value of the number of test repetitions, a test time may be undesirably prolonged.